1. Field of the Invention
The present invention relates to an amplification circuit that amplifies an input signal.
Priority is claimed on Japanese Patent Application No. 2010-096933, filed Apr. 20, 2010, the content of which is incorporated herein by reference.
2. Description of the Related Art
All patents, patent applications, patent publications, scientific articles, and the like, which will hereinafter be cited or identified in the present application, will hereby be incorporated by reference in their entirety in order to describe more fully the state of the art to which the present invention pertains.
Conventionally, as a method of detecting output signals from various sensors and the like with high accuracy, an instrumentation amplifier is known. For example, an instrumentation amplifier has been disclosed in “Refet Firat Yazicioglu, A 200 uW Eight-Channel EEG Acquisition ASIC for Ambulatory EEG Systems, IEEE JOURNAL SOLID-STATE CIRCUITS, Vol. 43, No. 12, DECEMBER 2008, pp. 3025-3038”. An instrumentation amplifier is required to amplify a difference voltage between input signals, remove common-mode voltages of the input signals, and achieve high input impedance.
Performance of removing the common-mode voltages of the input signals is defined as a common-mode rejection ratio. Thus, the common-mode rejection ratio is ideally infinite. However, the common-mode rejection ratio is limited to a finite value by an offset voltage of transistors of an input differential pair which constitutes the instrumentation amplifier. Therefore, it is impossible to equally control source-drain voltages of the transistors of the input differential pair, which are a factor of the offset voltage.
The configuration of the instrumentation amplifier, which is hereinafter referred to as an amplification circuit 200, disclosed in “Refet Firat Yazicioglu, A 200 uW Eight-Channel EEG Acquisition ASIC for Ambulatory EEG Systems, IEEE JOURNAL SOLID-STATE CIRCUITS, Vol. 43, No. 12, DECEMBER 2008, pp. 3025-3038” will be described. As shown in FIG. 3, the amplification circuit 200 includes an input differential pair including transistors M1 and M2, an output differential pair including a transistor M3 and a transistor M4, resistors R1 and R2, current conveyor circuits 101 and 102, level shift circuits 103 and 104, and transistors M5, M10, M15 and M16.
A positive input voltage VINP is supplied to a gate of the transistor M1 constituting the input differential pair. A negative input voltage VINN is supplied to a gate of the transistor M2 constituting the input differential pair. The resistor R1 is connected between a source of the transistor M1 and a source of the transistor M2 to generate a difference current ΔI corresponding to a difference voltage ΔVIN between the positive input voltage VINP and the negative input voltage VINN.
A drain of the transistor M3 constituting the output differential pair is connected between the source of the transistor M1 and one end of the resistor R1, and a negative output voltage VOUTN is supplied from a source of the transistor M3. A drain of the transistor M4 constituting the output differential pair is connected between the source of the transistor M2 and the other end of the resistor R1, and a positive output voltage VOUTP is supplied from a source of the transistor M4. Both ends of the resistor R2 are connected between the source of the transistor M3 and the source of the transistor M4, and the midpoint of the resistor R2 is connected to a reference voltage VCM. The difference current ΔI generated in the resistor R1 is supplied to the resistor R2.
In addition, the polarity (according to the conductive type of a channel) of the transistors M1 and M2 constituting the input differential pair is different from that of the transistors M3 and M4 constituting the output differential pair. In detail, the transistors M1 and M2 are P type transistors and the transistors M3 and M4 are N type transistors.
The transistor M5 supplies a bias current to the transistor M1 and the transistor M3 based on a first reference voltage BIAS1. The transistor M10 supplies a bias current to the transistor M2 and the transistor M4 based on the first reference voltage BIAS1.
The current conveyor circuit 101 includes transistors M6 to M9 and controls the bias current supplied to the transistor M1 to a constant value based on a second reference voltage BIAS2. The current conveyor circuit 102 includes transistors M11 to M14 and controls the bias current supplied to the transistor M2 to a constant value based on the second reference voltage BIAS2. The transistors M15 and M16 control the sum of the currents supplied to the transistor M3 and the transistor M4 to a constant value based on the second reference voltage BIAS2.
The level shift circuit 103 includes transistors M17 to M19 and is connected between a gate of the transistor M3 and the current conveyor circuit 101 to ensure an operating voltage of the transistor M3. The level shift circuit 104 includes transistors M20 to M22 and is connected between a gate of the transistor M4 and the current conveyor circuit 102 to ensure an operating voltage of the transistor M4.
In addition, the resistor R2 includes a resistor R3 connected between the source of the transistor M3 and the reference voltage VCM, and a resistor R4 connected between the source of the transistor M4 and the reference voltage VCM. It is assumed that the resistor R3 and the resistor R4 have the same resistance value. Hereinafter, it is assumed that the resistance values of the resistor R1, the resistor R2, the resistor R3 and the resistor R4 are R1, R2, R3 and R4, respectively. Furthermore, in the amplification circuit 200, a positive supply voltage is defined as VDD and a negative supply voltage is defined as VSS.
Next, the operation of the amplification circuit 200 will be described. In the amplification circuit 200, if the positive input voltage VINP is supplied to the gate of the transistor M1 and the negative input voltage VINN is supplied to the gate of the transistor M2, the difference voltage ΔVIN between the positive input voltage VINP and the negative input voltage VINN is supplied to the resistor R1. The resistor R1 generates the difference current ΔI(=ΔVIN/R1) corresponding to the difference voltage ΔVIN and the resistance value R1 of the resistor R1, thereby changing the values of the currents supplied from the transistor M5 and the transistor M10 to the transistor M3 and the transistor M4.
That is, the difference current ΔI is a part of the currents I which are normally supplied from the transistor M5 and the transistor M10 to the transistor M3 and the transistor M4. If the currents I that are supplied to the transistor M3 and the transistor M4 are defined as I3 and I4, the following Equations 1 to 3 are obtained.                When the positive input voltage VINP>the negative input voltage VINN,I3=I−ΔI I4=I+ΔI ΔI≠0  (1)        When the positive input voltage VINP<the negative input voltage VINN,I3=I+ΔI I4=I−ΔI ΔI≠0  (2)        When the positive input voltage VINP=the negative input voltage VINN,I3=I I4=I ΔI=0  (3)        
The currents I3 and I4 supplied to the transistor M3 and the transistor M4 are drawn into the transistor M15 and the transistor M16 supplying the same bias current. Therefore, the difference current ΔI generated when the positive input voltage VINP>the negative input voltage VINN or the positive input voltage VINP<the negative input voltage VINN is completely supplied to the resistor R2 having the midpoint connected to the reference voltage VCM.
Here, if the difference voltage between the positive output voltage VOUTP and the negative output voltage VOUTN is defined as ΔVOUT, the following Equations 4 to 9 are obtained.                When the positive input voltage VINP>the negative input voltage VINN,        
                                                                        V                OUTP                            =                            ⁢                                                V                  CM                                +                                  Δ                  ⁢                                                                          ⁢                  I                  ×                  R                  ⁢                                                                          ⁢                  4                                                                                                        =                            ⁢                                                V                  CM                                +                                                                            R                      ⁢                                                                                          ⁢                      4                                                              R                      ⁢                                                                                          ⁢                      1                                                        ⁢                  Δ                  ⁢                                                                          ⁢                                      V                    IN                                                                                                                          =                            ⁢                                                V                  CM                                +                                                                            R                      ⁢                                                                                          ⁢                      2                                                              2                      ×                      R                      ⁢                                                                                          ⁢                      1                                                        ⁢                  Δ                  ⁢                                                                          ⁢                                      V                    IN                                                                                                          (        4        )                                                                                    V                OUTN                            =                            ⁢                                                V                  CM                                -                                  Δ                  ⁢                                                                          ⁢                  I                  ×                  R                  ⁢                                                                          ⁢                  3                                                                                                        =                            ⁢                                                V                  CM                                -                                                                            R                      ⁢                                                                                          ⁢                      3                                                              R                      ⁢                                                                                          ⁢                      1                                                        ⁢                  Δ                  ⁢                                                                          ⁢                                      V                    In                                                                                                                          =                            ⁢                                                V                  CM                                -                                                                            R                      ⁢                                                                                          ⁢                      2                                                              2                      ×                      R                      ⁢                                                                                          ⁢                      1                                                        ⁢                  Δ                  ⁢                                                                          ⁢                                      V                    IN                                                                                                          (        5        )                                                                                    Δ                ⁢                                                                  ⁢                                  V                  OUT                                            =                            ⁢                                                V                  OUTP                                -                                  V                  OUTN                                                                                                        =                            ⁢                                                                    R                    ⁢                                                                                  ⁢                    2                                                        R                    ⁢                                                                                  ⁢                    1                                                  ⁢                Δ                ⁢                                                                  ⁢                                  V                  IN                                                                                        (        6        )                            When the positive input voltage VINP<the negative input voltage VINN,        
                                                                        V                OUTP                            =                            ⁢                                                V                  CM                                -                                  Δ                  ⁢                                                                          ⁢                  I                  ×                  R                  ⁢                                                                          ⁢                  4                                                                                                        =                            ⁢                                                V                  CM                                -                                                                            R                      ⁢                                                                                          ⁢                      4                                                              R                      ⁢                                                                                          ⁢                      1                                                        ⁢                  Δ                  ⁢                                                                          ⁢                                      V                    IN                                                                                                                          =                            ⁢                                                V                  CM                                -                                                                            R                      ⁢                                                                                          ⁢                      2                                                              2                      ×                      R                      ⁢                                                                                          ⁢                      1                                                        ⁢                  Δ                  ⁢                                                                          ⁢                                      V                    IN                                                                                                          (        7        )                                                                                    V                OUTN                            =                            ⁢                                                V                  CM                                +                                  Δ                  ⁢                                                                          ⁢                  I                  ×                  R                  ⁢                                                                          ⁢                  3                                                                                                        =                            ⁢                                                V                  CM                                +                                                                            R                      ⁢                                                                                          ⁢                      3                                                              R                      ⁢                                                                                          ⁢                      1                                                        ⁢                  Δ                  ⁢                                                                          ⁢                                      V                    IN                                                                                                                          =                            ⁢                                                V                  CM                                +                                                                            R                      ⁢                                                                                          ⁢                      2                                                              2                      ×                      R                      ⁢                                                                                          ⁢                      1                                                        ⁢                  Δ                  ⁢                                                                          ⁢                                      V                    IN                                                                                                          (        8        )                                                                                    Δ                ⁢                                                                  ⁢                                  V                  OUT                                            =                            ⁢                                                V                  OUTP                                -                                  V                  OUTN                                                                                                        =                            ⁢                                                -                                                            R                      ⁢                                                                                          ⁢                      2                                                              R                      ⁢                                                                                          ⁢                      1                                                                      ⁢                Δ                ⁢                                                                  ⁢                                  V                  IN                                                                                        (        9        )            
Consequently, the amplification circuit 200 can amplify the difference voltage ΔVIN between the positive input voltage VINP and the negative input voltage VINN according to the ratio of the resistances values of the resistor R1 and the resistor R2.
Next, the current conveyor circuit 101 will be described. When the source-drain voltage of the transistor M1 is defined as VDS1, the source voltage of the transistor M1 is defined as VS1, the drain voltage of the transistor M1 is defined as VD1, and the gate-source voltage of the transistor M1 is defined as VGS1, the current conveyor circuit 101 controls the source-drain voltage VDS1 of the transistor M1 as expressed by Equation 10.VDS1=VS1−VD1=VINP+VGS1−(VINP+VGS1−VGS6+VGS7)=VGS6−VGS7  (10)
Likewise, when the source-drain voltage of the transistor M2 is defined as VDS2, the source voltage of the transistor M2 is defined as VS2, the drain voltage of the transistor M2 is defined as VD2, and the gate-source voltage of the transistor M2 is defined as VGS2, the current conveyor circuit 102 controls the source-drain voltage VDS2 of the transistor M2 as expressed by Equation 11.VDS2=VS2−VD2=VINN+VGS2−(VINN+VGS2−VGS11+VGS12)=VGS11−VGS12  (11)
Consequently, the current conveyor circuits 101 and 102 can control the source-drain voltage VDS1 of the transistor M1 and the source-drain voltage VDS2 of the transistor M2 to constant values.
It is known that, in general, the common-mode rejection ratio of the amplification circuit is deteriorated when an offset voltage of an amplification circuit increases. The offset voltage (a difference voltage between a gate and a source of an input differential pair) of the amplification circuit is determined in proportion to element sizes if the element sizes and operation conditions (a source-drain voltage and a source-drain current) of the input differential pair constituting the amplification circuit are the same. When the operation conditions of the input differential pair are different from each other, the offset voltage is determined in proportion to the operation conditions.
As mentioned above, the common-mode rejection ratio is limited to a finite value by an offset voltage of transistors of an input differential pair. Therefore, it is essential to equally control the source-drain voltages and the source-drain currents of the transistors of the input differential pair, which are a factor of the offset voltage. In the amplification circuit 200, the source-drain voltage VDS1 and the source-drain current IDS1 of the transistor M1 and the source-drain voltage VDS2 and the source-drain current IDS2 of the transistor M2 can be controlled to constant values by the current conveyor circuits 101 and 102, respectively. Consequently, the offset voltages generated in the transistors M1 and M2 can be reduced, so that the common-mode rejection ratio of the amplification circuit 200 can be improved. Here, the source-drain voltage of the transistor is changed by the source-drain current. Therefore, in order to equally set the source-drain voltage of the transistors constituting the input differential pair, it is also necessary to equally set the source-drain current.
Next, the level shift circuit 103 will be described. When the maximum output voltage+of the amplification circuit 200 is defined as VOUTMAX, the source-drain voltages of the transistor M1, the transistor M3 and the transistor M7 are defined as VDS1, VDS3 and VDS7, and the gate-source voltages of the transistor M1, the transistor M3, the transistor M18 and the transistor M9 are defined as VGS1, VGS3, VGS18 and VGS19, the VOUTMAX is expressed by Equations 12 and 13.VOUTMAX=VINP−VGS1=VDS1+VDS7−VGS19+VGS18−VGS3  (12)VOUTMAX′=VINP+VINP+VGS1−VDS3  (13)
Here, as an example, when VDD is set to 3 V and VINP is set to ½VDD, that is 1.5 V, with respect to Equations 12 and 13 and design parameters of the transistor M1, the transistor M3, the transistor M7, the transistor M18 and the transistor M19 are set as shown in FIG. 4, Equations 14 and 15 are obtained.
                              V          OUTMAX                =                                            V              INP                        +                          V                              th                ⁢                                                                  ⁢                1                                      -                                                            2                  ×                                      I                    7                                                                    β                  ⁢                                                                          ⁢                                                            W                      7                                                              L                      7                                                                                            +                          V                              th                ⁢                                                                  ⁢                19                                      +                                                            2                  ×                                      I                    19                                                                    β                  ⁢                                                                          ⁢                                                            W                      19                                                              L                      19                                                                                            +                          V                              th                ⁢                                                                  ⁢                18                                      +                                                            2                  ×                                      I                    18                                                                    β                  ⁢                                                                          ⁢                                                            W                      18                                                              L                      18                                                                                            -                          (                                                V                                      th                    ⁢                                                                                  ⁢                    3                                                  +                                                                            2                      ×                                              I                        3                                                                                    β                      ⁢                                                                                          ⁢                                                                        W                          3                                                                          L                          3                                                                                                                                )                                >                      V            DD                                              (        14        )                                                          ⁢                              V            OUTMAX            ′                    =                                                    V                INP                            +                              V                                  th                  ⁢                                                                          ⁢                  1                                            -                                                                    2                    ×                                          I                      1                                                                            β                    ⁢                                                                                  ⁢                                                                  W                        1                                                                    L                        1                                                                                                        -                                                                    2                    ×                                          I                      3                                                                            β                    ⁢                                                                                  ⁢                                                                  W                        3                                                                    L                        3                                                                                                                  =                          2.28              ⁢                                                          ⁢              V                                                          (        15        )            
The VOUTMAX is determined by the smaller of the values calculated by Equations 14 and 15 above. Therefore, the VOUTMAX′ calculated by Equation 15 is the maximum output voltage+of the amplification circuit 200. Meanwhile, if a common connection point between the drain of the transistor M7 and the drain of the transistor M9 in the current conveyor circuit 101 is directly connected to the gate of the transistor M3 without the level shift circuit 103, Equation 14 is changed to Equation 16.
                                                                        V                OUTMAX                ″                            =                            ⁢                                                V                  INP                                +                                  V                                      th                    ⁢                                                                                  ⁢                    1                                                  -                                                                            2                      ×                                              I                        7                                                                                    β                      ⁢                                                                                          ⁢                                                                        W                          7                                                                          L                          7                                                                                                                    -                                  (                                                            V                                              th                        ⁢                                                                                                  ⁢                        3                                                              +                                                                                            2                          ×                                                      I                            3                                                                                                    β                          ⁢                                                                                                          ⁢                                                                                    W                              3                                                                                      L                              3                                                                                                                                                            )                                                                                                        =                            ⁢                              1.64                ⁢                                                                  ⁢                V                                                                        (        16        )            
By Equations 15 and 16, the level shift circuit 103 can increase the maximum output voltage+of the amplification circuit 200. In addition, although not described herein, the level shift circuit 104 can increase the maximum output voltage+of the amplification circuit 200 because it is equivalent to the level shift circuit 103.